The maximum electric field E.sub.M, in a MOSFET arises near the drain when the device is operating in a saturated condition. E.sub.M is greatly increased as device dimensions are reduced. These high electric fields cause electrons in the channel to gain kinetic energy and become "hot" since the energy distribution of the electrons is shifted to a higher value than that of the electrons which are in thermal equilibrium with the lattice. The electrons generally become hot in the vicinity of the drain edge of the channel where the E.sub.M arises. Hot electrons are damaging to device performance since such electrons can lose energy by impact ionization which generates electron-hole pairs. Electron-hole pair generation can lead to a form of avalanche breakdown. In addition, the hot holes and electrons can overcome the potential energy barrier between silicon substrate and a silicon dioxide layer overlying the substrate, thereby causing hot carriers to become injected into the gate oxide. Problems arising from hot carrier injection into the gate oxide include generation of a gate current, generation of a positive trapped charge which can permanently increase the threshold voltage (V.sub.T) of the transistor. These problems are manifest as a decrease in saturation current, decrease of the transistor transconductance and a continual reduction in device performance caused by trapped charge accumulation.
Thus, hot-carrier effects cause unacceptable performance degradation in MOS devices built with conventional drain structures when channel lengths are short. To remedy this problem, alternative drain structures such as lightly doped drain (LDD) structures have been developed. Lightly doped drains absorb some of the potential energy into the drain and thus reduce E.sub.M.
In the typical LDD structure, the drain is formed by two implants. One implant is self-aligned to the gate electrode. A second implant is self-aligned to the gate electrode on which two oxide sidewall spacers are formed. The purpose of the lightly doped first implant is to form a lightly doped section of the drain at the edge near the channel. The value of E.sub.M is reduced by about thirty to forty percent using this structure because the voltage drop is shared by the drain and the channel. In a typical non-LDD drain structure, almost the entire voltage drop occurs across the lightly doped channel region. The heavier second dose forms a low resistivity region of the drain, which is merged with the lightly doped region. Since the heavier dose is removed from the channel in an LDD structure than in a conventional structure, the heavily doped region of the drain can be made deeper without impacting device operation. The increased junction depth lowers the sheet resistance and the contact resistance of the drain.
A disadvantage of an LDD structure is an increased parasitic resistance of the source and drain regions caused by the lightly doped regions of the drain. The increased parasitic resistance causes a greater power dissipation for a constant applied voltage.
Further improvements in transistor reliability and performance for exceedingly smaller devices are achieved by transistors having an asymmetric LDD structure. Parasitic resistance at the source side of an LDD structure transistor induces a serious decrease in drain current. The reduced drain current is explained by an effective gate voltage drop from self-biased negative feedback. On the drain side of the transistor, drain current is not appreciably affected by the drain side parasitic resistance when the transistor is operating in the saturation region. Therefore, it is important to form the source and drain LDD structures separately, having a lightly doped drain region but no LDD structure in the source region, to achieve high-performance MOSFET operation.
One method for fabricating a transistor having an asymmetric LDD structure is taught by T. N. Buti et al in "Asymmetric Halo Source GOLD drain (HS-GOLD) Deep Sub-half Micron n-MOSFET Design for Reliability and Performance", International Electron Devices Meeting (IEDM) Technical Digest, p. 617, 1989. In this method, large-tilt implantation is used to form a gate-overlapped LDD region at the drain electrode alone. A halo (punch through stopper) is used at the source, but not at the drain. A disadvantage of this method is that a large-tilt implant is required, which greatly increases manufacturing complexity. In addition, to form many LDD structure transistors on a silicon wafer, multiple large-tilt implants are performed at various wafer orientations, further increasing manufacturing complexity and costs.
Another method for fabricating a transistor having an asymmetric LDD structure is disclosed by T. Horiuchi et al in "An Asymmetric Sidewall Process for High Performance LDD MOSFET's", IEEE Transactions on Electron Devices, Vol. 41, No. 2, p. 186, February 1994. Using this method an asymmetric LDD sidewall spacer technology achieves a high drivability LDD MOSFET without sacrificing hot carrier immunity. The asymmetric spacer is fabricated using a selective oxide deposition technique in which oxide is selectively deposited by a nonstandard liquid phase oxide deposition (LPD) process at the surface of the oxide and polysilicon surface. Then, a sidewall is formed by reactive ion etching. This technique is a standard process except for the unconventional LDD sidewall formation process. It is disadvantageous and costly to utilize a nonstandard process step.